A phase-locked loop (PLL) is a circuit designed to lock onto a specific phase. Anyone familiar with the principles of automatic control systems knows that it’s a classic feedback control mechanism. By using an external reference signal, the PLL precisely adjusts both the frequency and phase of an internal oscillating signal, enabling the output signal to automatically track the input signal’s frequency—making it ideal for closed-loop tracking applications. In radio transmission, the PLL is a key technique for achieving stable frequencies. It typically consists of two main components: a Voltage-Controlled Oscillator (VCO), which generates an initial signal, and a PLL IC (Phase-Locked Loop Integrated Circuit). A portion of the VCO’s output serves as the final output signal, while another part is divided down and compared in phase with the local oscillator signal produced by the PLL IC. To maintain a constant frequency, the system ensures that the phase difference remains unchanged. If any phase discrepancy occurs, the voltage output from the PLL IC adjusts accordingly, feeding back into the VCO until the phase difference is restored, thus achieving phase locking. Essentially, a PLL is a closed-loop electronic circuit that guarantees the controlled oscillator’s frequency and phase remain locked in a precise relationship with the input signal.
Analogy explanation
When we first started learning to drive, our eyes acted like a detector, constantly monitoring whether the car’s direction of travel (feedback) matched the road ahead (input). Any discrepancy between the two was sent to the brain for quick assessment, which then instructed our hands to turn the steering wheel—transforming that physical action into a corresponding change in the car’s direction of movement.
 

We continuously adjust the steering wheel through this closed-loop process, ensuring the car stays on the right path.
The phase-locked loop typically consists of three main components in its forward path: a phase detector (PD), a loop filter (LF), and a voltage-controlled oscillator (VCO). A frequency-phase feedback loop is formed by a frequency divider.
The phase-locked loop works by detecting the phase difference between the input and output signals, then converting this detected phase difference into a voltage signal via a phase detector. After being filtered by a low-pass filter, this voltage serves as the control signal for the voltage-controlled oscillator, thereby regulating the oscillator's output frequency. Finally, the oscillator's output frequency and phase are fed back to the phase detector through the feedback loop. 

During operation, when the frequency of the output signal proportionally mirrors that of the input signal, the output voltage maintains a fixed phase difference relative to the input voltage—effectively "locking" their phases together.
Introduction
A phase-locked loop is a circuit or module used in communication receivers to process incoming signals and extract the phase information of a specific clock. Alternatively, it generates an imitation of the received signal’s clock, ensuring that the two signals appear synchronized—or coherent—from a certain perspective. Because, under locked conditions (after successful capture), the generated clock signal typically exhibits a slight phase difference relative to the clock embedded within the received signal, it’s aptly referred to as a "phase-locked loop."
The phase-locked loop consists of a phase detector, a loop filter, and a voltage-controlled oscillator. The phase detector compares the phase difference between the input signal \( U_i \) and the output signal \( U_o \), generating an error voltage \( U_d \). Any noise or interference components in \( U_d \) are filtered out by the low-pass characteristics of the loop filter, resulting in a control voltage \( U_c \) that feeds into the voltage-controlled oscillator (VCO). This control voltage \( U_c \) adjusts the VCO's output oscillation frequency \( f_o \), pulling it closer to the loop input signal frequency \( f_i \). When \( f_o \) eventually matches \( f_i \), the loop locks—this is known as "locking." Once locked, the DC control voltage sustaining this state is provided by the phase detector itself; hence, there remains a small phase difference between the two input signals fed to the phase detector.
PLL: Phase-Locked Loop, or phase synchronization circuit, is used to synchronize and align clock signals, enabling memory to access data accurately.
Direct Digital Frequency Synthesis (DDS) is a novel frequency synthesis technique that has revolutionized the field of frequency generation. The concept of DDS was first introduced in 1971 by JOSEPH TIERNEY and three other researchers. However, due to the technological limitations of the time—specifically in microelectronics and digital signal processing—DDS did not receive the attention it deserved. Today, as the demand for advanced electronic solutions continues to grow, coupled with significant advancements in digital integrated circuits and microelectronic technologies, DDS is increasingly demonstrating its remarkable advantages.
DDS is a fully digital frequency synthesizer composed of a phase accumulator, waveform ROM, D/A converter, and low-pass filter. Once the clock frequency is set, the output signal’s frequency is determined by the frequency controller; the frequency resolution depends on the number of bits in the accumulator, while the phase resolution is influenced by the number of address lines in the ROM. Additionally, the amplitude quantization noise level is affected by both the data word length of the ROM and the bit resolution of the D/A converter.
Advantages
DDS has the following advantages:
⑴ High frequency resolution with a large number of output frequencies, reaching up to N frequency points (where N is the number of bits in the phase accumulator).
⑵ Fast frequency switching, with speeds reaching the microsecond level;
⑶ Phase remains continuous during frequency switching;
⑷ Can output broadband orthogonal signals;
⑸ Features low phase noise and effectively improves the phase noise of the reference frequency source;
⑹ Can generate arbitrary waveforms;
(7)Fully digital implementation ensures ease of integration, resulting in compact size and lightweight designs. As a result, since the 1980s, countries around the world have been developing their own DDS products, such as the Q2334 and Q2220 from U.S.-based QUALCOMM, the STEL-1175 and STEL-1180 from STANFORD, and the AD7008, AD9850, and AD9854 from AD. These DDS chips offer clock frequencies ranging from tens to hundreds of megahertz, with variations from basic functionality to advanced models that integrate D/A converters and even quadrature modulators.
PLL: Phase Locked Logic – Phase-Synchronized Logic.
The purpose of a phase-locked loop is to establish carrier or bit synchronization between the transmitting and receiving communication parties. Since its operation involves an automatic frequency (or phase) adjustment through a closed-loop mechanism, it’s called a "loop." Phase-locked loops are categorized into two types: analog phase-locked loops and digital phase-locked loops.
Uses
In the late 1950s, with the advancement of space technology, phase-locked loops began to be used for tracking, telemetry, and remote control of spaceflight targets. By the early 1960s, as digital communication systems gained momentum, the applications of phase-locked loops expanded further—such as extracting the reference carrier for coherent demodulation and establishing bit synchronization. Additionally, phase-locked frequency discriminators capable of handling threshold-extension techniques were also developed in the early 1960s. In the realm of electronic instrumentation, phase-locked loops played a critical role in devices like frequency synthesizers and phase meters.
Currently, phase-locked loop technology is primarily applied in three key areas: first, signal modulation and demodulation; second, signal frequency modulation and demodulation; and third, signal frequency synthesis circuits.
Classification and Operating Principle
Basic working principle
The voltage-controlled oscillator generates a signal—part of which serves as the output, while the other portion is fed into a phase comparator, where it’s compared against the local oscillator signal produced by the PLL IC after frequency division. To maintain a constant frequency, the phase difference must remain unchanged. If any phase difference occurs, the voltage output of the PLL IC adjusts accordingly, feeding back to control the VCO until the phase difference stabilizes again—thus achieving frequency locking! Ultimately, this closed-loop electronic circuit ensures that both the frequency and phase of the controlled oscillator remain locked in a precise relationship with the input signal.
How a Phase-Locked Loop Works – Simulation
The analog phase-locked loop primarily consists of a phase reference extraction circuit, a voltage-controlled oscillator, a phase comparator, and a control circuit. The voltage-controlled oscillator outputs an amplitude-stable signal that closely matches the desired frequency. This signal is simultaneously fed into the phase comparator along with the reference signal extracted from the input by the phase reference extraction circuit. The error generated by this comparison is then processed by the control circuit, causing the frequency of the voltage-controlled oscillator to continuously adjust—moving in the direction that minimizes the magnitude of the error—thereby achieving phase locking and ultimately enabling synchronization.
How Digital Phase-Locked Loops Work
The digital phase-locked loop primarily consists of a phase reference extraction circuit, a crystal oscillator, a frequency divider, a phase comparator, and a pulse suppression gate. The signal output from the frequency divider has a frequency that closely matches the desired frequency. This signal, along with the phase reference extracted from the input signal, is simultaneously fed into the phase comparator. If the comparison reveals that the local frequency is too high, the suppression gate removes one input pulse from the frequency divider, effectively lowering the local oscillation frequency. Conversely, if the comparison indicates that the local frequency is too low, the gate inserts an additional pulse between the two existing input pulses at the divider’s input, thereby increasing the local oscillation frequency—and ultimately achieving synchronization.