Jitter, as one of the key metrics for 12G-SDI, ranks alongside rise/fall time and amplitude as the three major indicators for SDI—and also serves as a critical benchmark for all high-speed signals, helping to assess their stability and reliability. Analyzing jitter, however, is challenging due to the multitude of factors contributing to its generation. To begin with, we’ll examine jitter formation by focusing on board-level parameters.
The parasitic parameters of 12G-SDI (or any high-speed signal, for that matter) have always been a major headache for hardware engineers. The presence of parasitic resistance, parasitic inductance, and parasitic capacitance constantly threatens to drag high-speed signals into instability, leading to increased rise times, slower edges, reduced amplitude, and the generation of significant jitter—ultimately resulting in bit errors.
At standard atmospheric pressure and temperature, parasitic parameters cannot be eliminated. For now, we’ll set aside the analysis of intrinsic changes in metals and fibers under superconducting conditions. We can gain a clearer understanding by examining a simple formula—take, for instance, the board-level parasitic capacitance equation: "C (pF) = W × L × Er0 × Er1 / d," where: - W = wiring width, - L = wire length, - Er0 = dielectric constant of air, - Er1 = dielectric constant of the circuit board, - d = spacing between wires. As you can see, the interplay among these multiple parameters ultimately determines the value of parasitic capacitance. Now, when signals change at high speeds, crosstalk occurs, inducing coupling currents in adjacent traces: "I (A) = C × (dV/dt)." However, if we attempt to mitigate this transient current, we inevitably encounter new challenges. For example, altering the source-side impedance will invariably affect the transmission line’s characteristic impedance, leading to signal reflections that cause jitter. Alternatively, increasing inductance might suppress the formation of transient currents—but at the same time, it could give rise to damped oscillations in the magnetic field, which proves particularly detrimental for high-speed signals. On top of these effects, the combined influence of parasitic resistance and parasitic inductance further complicates matters. As a result, the 12G-SDI board exhibits numerous reflection points, significantly amplifying signal jitter. This jitter then propagates backward along the transmission path, cascading and accumulating as it moves downstream.
 

However, source jitter isn’t the only jitter source in 12G-SDI; the primary source of jitter in SDI still comes from the timing deviation of the ideal duty-cycle periodic signal, known as TIE (Time Interval Error).
Unlike low-speed signals such as 3G/HD/SD-SDI, 12G-SDI operates at a significantly higher clock frequency, making the transmission medium’s impact much more pronounced. At this high frequency, board-level parasitic parameters, crosstalk, impedance mismatches, and even non-standard connectors or improper soldering techniques at endpoints can all contribute to substantial timing jitter generation in 12G-SDI. As a result, the TIE exhibits a broad frequency-domain coverage, complicating the effective measurement and control of jitter ranges. To address this, SMPTE 2082-1:2015 defines jitter ranging from 10 Hz (the lower edge of the timing jitter band) up to 1.2 GHz (the upper band edge) as **Timing Jitter**, while jitter between 100 kHz (the lower edge of the alignment jitter band) and 1.2 GHz (the upper band edge) is classified as **Alignment Jitter**. Measuring jitter induced by TIE remains the most efficient method for testing 12G-SDI today, and it is also well-suited for evaluating 6G/3G/HD/SD-SDI signals, as well as TS streams encoded according to terrestrial digital broadcasting standards like DVB-ASI (supporting MPEG2, H.264, AVS+, and other formats).

It can be seen that timing jitter, due to its broader frequency-domain coverage, results in higher jitter values compared to alignment jitter. According to the ST2082-1:2015 standard, the timing jitter for 12G-SDI should be less than 2 UI (168 ps), while the alignment jitter should remain below 0.3 UI (28 ps).
Here, we introduce two additional terms: deterministic jitter and random jitter.
Due to the vast number of factors that contribute to jitter, we categorize it for convenience: Jitter with repetitive periodicity and predictable behavior is referred to as deterministic jitter, while jitter that varies randomly over time, follows a Gaussian distribution, and lacks predictability is called random jitter. Since random jitter cannot be effectively filtered or eliminated, it continues to influence measurements of 12G-SDI jitter, causing test values to fluctuate and potentially exceed ST standards. Therefore, we also recommend product designers optimize board-level designs as much as possible—matching impedance characteristics—to enhance 12G-SDI jitter margins and minimize output jitter.
Among all SMPTE SDI standards, the alignment jitter for 12G-SDI has been relaxed to 0.3 UI for the first time—though this represents a 0.1 UI increase compared to the 0.2 UI standard of 3G-SDI, it still remains four times greater than the speed of 3G-SDI. Thus, even with this slight increase, the additional margin for jitter remains negligible. As a result, effectively reducing signal jitter continues to pose the most significant challenge for product designers.

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