ES = (B_sent)'+(B_sent > B_received)B_received
Introduction
The echo suppressor typically includes: a voice signal level detection and amplification circuit for both receive and transmit paths, comparators, echo suppression control logic circuits, a transmit channel switch ES, a receive channel switch RP, and 60dB and 6dB attenuators, among other components. A schematic diagram illustrating the circuitry of an echo suppressor is provided below.

1. When the satellite communication line is idle, the ES and RP switches close, ensuring zero loss in both the transmit and receive channels.
2. When the user at end A initiates a call, the voice signal is transmitted via the A-end transmission channel, satellite link, and B-end reception channel to the user at end B. Once the echo canceller at end B detects a voice signal on the reception channel, it immediately activates switch ES on the transmission channel, triggering the 60-dB ATT attenuator to block the echo signal from traveling back through the transmission channel to end A. As soon as the received signal disappears, switch ES automatically returns to its original state.
3. When the user at end A is silent while the user at end B is speaking, the echo canceller at end B detects and amplifies the local voice signal being transmitted. In this scenario, the ES switch should be activated, the RP switch on the receive channel should be turned off, and a 6-dB ATT attenuator should be inserted in series on the receive channel—resulting in a 6-dB improvement in the local end’s ability to suppress echo interference.
4. When the B-end user is receiving a call from the A-end user, the B-end user may also initiate their own talk at any moment—this represents a scenario where both parties are speaking simultaneously. In this case, if the echo suppressor’s detection circuit identifies that the speech signal level exceeds the received phone signal level, it should trigger both switches ES and RP to open simultaneously. As a result, the echo suppressors at both ends (A and B) will provide a 66-dB attenuation for both the speech signal and any echo interference signals.
Function
The output ES and RP of the echo suppression control logic circuit in the echo suppressor, along with their logical relationship to the inputs Btx, Btx, and Brx, were simplified using a Karnaugh map, resulting in the following relationships.

ES = (B sends)'+(B sends > B receive)B receive

RP = B sends

In the diagram, HC2 and IC21 detect the received voice signal, while HC2 and IC22 detect the transmitted voice signal. After detection, the resulting DC signals—obtained through integration—are compared separately with a fixed voltage in the IC7 comparator. The outputs from these comparisons are labeled R and T, respectively, and both are sent to the echo suppression control logic circuit.
The two types of audio signals, after being detected and integrated, produce DC signals that are then compared against each other in the IC8 comparator. The output is represented by R/T. 

IC10 is an adder circuit built using the 4558 operational amplifier, which adds the transmitted and received voice signals. Its output splits into two paths: one path feeds into HC3 for detection, then gets compared with a fixed voltage using the IC9 comparator—this process extracts the T+R signal. The other path is routed to a single-tone notch filter/tonal oscillator circuit constructed from IC24 S3526P, which precisely controls the output of a tone signal at a specific frequency. This signal is subsequently amplified, detected, and compared, ultimately producing the (T+R) single-tone output.
In the diagram, IC39 through IC42 4520B are dual to hexadecimal up-counters. The R terminals of IC39 and IC41 4520B are externally connected to the +5V power supply via resistors. Therefore, when either R or (T+R) is held high individually, the outputs Q4 at pin 11 of IC39 and Q6 at pin 13 of IC41 go low. Only when either R or (T+R) is pulled low does the 4520B begin counting the 250Hz oscillator signal. Once Q4 or Q6 transitions to "1," the counter stops counting entirely and remains latched in its current state—holding a high level. Notably, the output of the 4520B exhibits a delay characteristic in response to the individual R or (T+R) input signals. This feature effectively prevents the clipping of the first syllable that might otherwise occur due to echo suppressors when satellite lines are engaged in two-way communication.  

When any of the following conditions occur, pin 15 of the IC19 HI-5043 switch goes high, causing the contacts between pins 16 and 1 to open while those between pins 4 and 3 close, activating the channel ATT 60dB attenuator.
1. When the R signal is at a low level, approximately 64 ms later, IC39 4520B Q4 becomes 1;
2. The T/R signal is high, the R signal is low, 4013 Q’ = 1, and the T signal is high;
3. When the (T+R) signal is low, Q6 = 0 and 4013 R = 0; alternatively, when the single (T+R) signal is low, IC41 Q6 = 1 and 4013 S = 1.
When any of the following conditions occur, pin 10 of IC19 Hl-5043 switch goes high, the connection between pins 8 and 9 breaks, while the connection between pins 6 and 5 closes—activating the 6 dB ATT attenuator in the receive channel.
1. When the T/R signal is at a low level, after 256 ms, IC40 4520B Q6 becomes 1;
2. The T signal is low, the R signal is low, 40B R = 1, and Q = 0;
3. When the T+R signal is low, IC42 4520B Q = 0 and 4013B R = 0; when the single (T+R) signal goes low, after 256 ms, IC41 4520B Q6 becomes 1, 4013B S turns to 1, and Q' resets to 0.