The signal return path, also known as the return current, refers to how high-speed digital signals travel: they flow from the driver through the PCB transmission line toward the load, and then, via the shortest possible path—either along ground or power—to return back to the driver end. This returning signal on the ground or power plane is what we call the signal return path. As Dr. Johnson explains in his book, high-frequency signal transmission essentially involves charging the dielectric capacitance that exists between the transmission line and the DC planes. SI analysis focuses precisely on the electromagnetic characteristics of this surrounding field, as well as the coupling mechanisms between these elements.
Example explanation:

IC1 is the signal output terminal, while IC2 serves as the signal input terminal (to simplify the PCB model, we assume the receiver includes a pull-down resistor internally). The third layer is the ground plane. Both IC1 and IC2 share their ground connections, which are sourced from the third-layer ground plane. In the top-right corner of the top layer, there’s a power plane connected to the positive supply voltage. C1 and C2 are decoupling capacitors specifically placed near IC1 and IC2, respectively. As shown in the diagram, the power and ground pins of the chips correspond to the power and ground supplies for both the transmitting and receiving signal terminals.
At low frequencies, if the S1 pin outputs a high level, the entire current loop flows from the power supply, through the wire connected to the VCC power plane, then follows the orange path into IC1, exits via the S1 pin, and continues—without any second-layer wiring—through the R1 pin into IC2, before finally returning to the GND layer and completing the circuit back to the negative terminal of the power supply via the red path.
However, at high frequencies, the distributed characteristics of the PCB can significantly impact the signal. What we commonly refer to as "ground return current" is a frequent issue encountered in high-frequency signals. Since high-frequency signals feature rapid voltage and current changes—but with very short periods—these signals don’t require much energy overall. As a result, the chip draws power directly from the decoupling capacitor closest to it. When C1 is sufficiently large and responds quickly enough (typically achieved with ceramic capacitors, which have much lower ESR values compared to tantalum capacitors), the orange path on the top layer and the red path on the GND layer effectively become negligible. In other words, while there is still an overall current flowing to supply the entire board, this current doesn’t correspond to the specific signal shown in the diagram.
Therefore, following the circuit configuration shown in the diagram, the complete current path is as follows: from the positive terminal of C1 → VCC pin of IC1 → switch S1 → signal line L2 → resistor R1 → GND pin of IC2 → via hole → yellow path on the GND layer → via hole → and finally to the negative terminal of the capacitor. As you can see, there’s a brown-colored equivalent current flowing vertically, which induces a magnetic field in the surrounding area. At the same time, this looped current path can easily couple external interference signals into the circuit. Now, imagine that the signal depicted in the diagram represents an 8-bit data bus running parallel to a clock signal, both powered by the same chip and supplied from the same power source. In this scenario, the current return paths for both the clock and data lines would be identical. If the data lines simultaneously toggle in the same direction—either all high or all low—the result could induce a significant reverse current in the clock signal. And if the clock line isn’t properly terminated or matched, this crosstalk could severely disrupt—or even completely ruin—the integrity of the clock signal. Importantly, the strength of this crosstalk doesn’t depend solely on the absolute voltage levels of the interfering source; instead, it’s directly proportional to the rate at which the current changes over time (dI/dt). For a purely resistive load, the crosstalk current is given by the formula: \[ dI/dt = \frac{dV}{T_{10\%-90\%} \times R} \] Here, \( dI/dt \) represents the rate of current change, \( dV \) refers to the amplitude of the interfering signal, and \( R \) denotes the load resistance. Note that if the load is capacitive rather than resistive, the relationship between \( dI/dt \) and the rise/fall time (\( T_{10\%-90\%} \)) becomes inversely proportional to the square of that time interval. From this equation, we can conclude that slower signals aren’t necessarily less susceptible to crosstalk than faster ones. In fact, what truly matters is not just the frequency of the signal but also its edge steepness. Signals with very sharp rising or falling edges contain rich harmonic content, generating substantial amplitudes at multiple frequency multiples. This highlights the importance of carefully selecting components during circuit design. Choosing chips with excessively fast switching speeds might seem appealing due to their performance benefits, but such devices often come at a higher cost—and more importantly, they can exacerbate crosstalk issues and complicate electromagnetic compatibility (EMC) challenges.
Any adjacent power layer or other plane can serve as the return path for a signal, provided there are appropriate capacitors at both ends of the signal to offer a low-impedance path to GND. In typical applications, the IO power supplies for the transmitting and receiving chips are often identical, and each supply is usually paired with a decoupling capacitor—typically ranging from 0.01 to 0.1 µF—connected between the power pin and ground. Importantly, these decoupling capacitors are positioned right at the signal’s endpoints, making the return current flow through the power plane highly efficient, second only to the effectiveness of the ground plane itself. However, if another power plane is used as the return path instead, there’s often no low-impedance connection directly to ground at the signal’s ends. As a result, the induced currents in the adjacent plane will seek out the nearest available decoupling capacitor to return to ground. If this "nearest capacitor" happens to be located far from either the signal’s source or destination, the return current must travel a significant distance—effectively "crossing continents"—to establish a complete loop. Crucially, this extended return path inadvertently becomes shared by neighboring signals as well, creating an unintended common-return path that introduces crosstalk between those signals. In essence, this shared return path mimics the effects of common-mode interference, ultimately leading to signal-to-signal crosstalk.
For situations where unavoidable power-domain splits occur, you can bridge across the split using a capacitor or an RC high-pass filter (e.g., a 10-ohm resistor in series with a 680pF capacitor—though the exact values will depend on your specific signal type). The purpose is to provide a high-frequency return path while effectively isolating low-frequency crosstalk between the adjacent planes. This approach may even involve placing capacitors directly between power planes, which might sound unconventional at first—but rest assured, it’s highly effective. If certain design guidelines explicitly prohibit this practice, you can instead route capacitors from each plane separately to ground at the split point.
For cases where other planes are borrowed for return current paths, it’s best to add a few small capacitors to ground at appropriate points along the signal traces, providing an additional return path. However, this approach is often difficult to implement, as the surface space near the terminals is usually already occupied by matching resistors and decoupling capacitors for the chip.